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4 w, gaas, phemt, mmic power amplifier, 5.5 ghz to 8.5 ghz data sheet HMC1121 rev. a document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 ?2016C2017 analog devices, inc. all rights reserved. technical support www.analog.com features high saturated output power (p sat ): 36.5 dbm at 30% power added efficiency (pae) high output third-order intercept (ip3): 44 dbm typical high gain: 28 db typical high output power for 1 db compression (p1db): 36 dbm typical total supply current: 2200 ma at 7 v 40-lead, 6 mm 6 mm lfcsp package: 36 mm 2 applications point to point radios point to multipoint radios very small aperture terminals (vsats) and satellite communications (satcoms) military electronic warfare (ew) and electronic counter measures (ecm) functional block diagram package base 22 2 1 4 5 3 1 2 1 1 nic nic nic nic rfin 6 7 nic nic 8 nic 9 10 nic nic nic nic 21 23 v ref 24 v det 25 nic 26 rfout 27 nic 28 nic 29 nic 30 nic nic nic 1 5 v dd3 1 4 v gg3 1 3 nic 1 6 nic 1 7 v gg4 1 8 nic 1 9 2 0 v dd4 nic 3 2 3 1 v dd2 nic 3 3 nic 3 4 v gg2 3 5 nic 3 6 v dd1 3 7 v gg1 3 8 nic 3 9 4 0 nic nic HMC1121 13529-001 figure 1. general description the HMC1121 is a three-stage, gallium arsenide (gaas), pseudomorphic high electron mobility transfer (phemt), monolithic microwave integrated circuit (mmic), 4 w power amplifier with an integrated temperature compensated on-chip power detector that operates between 5.5 ghz and 8.5 ghz. the HMC1121 provides 28 db of gain, 44 dbm output ip3, and 36.5 dbm of saturated output power at 30% pae from a 7 v power supply. the HMC1121 exhibits excellent linearity and it is optimized for high capacity, point to point and point to multipoint radio systems. the amplifier configuration and high gain make it an excellent candidate for last stage signal amplification preceding the antenna. ideal for supporting higher volume applications, the HMC1121 is provided in a 40-lead lfcsp package.
HMC1121 data sheet rev. a | page 2 of 15 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 functional block diagram .............................................................. 1 general description ......................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 electrical specifications ............................................................... 3 absolute maximum ratings ............................................................ 4 esd caution .................................................................................. 4 pin configuration and function descriptions ............................. 5 interface schematics ..................................................................... 6 typical performance characteristics ..............................................7 theory of operation ...................................................................... 11 applications information .............................................................. 12 recommended bias sequence .................................................. 12 typical application c ircuit ....................................................... 12 evaluation board ............................................................................ 13 bill of materials ........................................................................... 13 evaluation bo ard schematic ..................................................... 14 outline dimensions ....................................................................... 15 ordering guide .......................................................................... 15 revision history 10 /2017 rev. 0 to r ev. a changes to figure 32 ...................................................................... 11 updated outline dimensions ....................................................... 15 changes to ordering guide .......................................................... 15 7 /2016 revision 0 : initial version
data sheet HMC1121 rev. a | page 3 of 15 specifications electrical specifica tions t a = 25c, v dd = v dd1 = v dd2 = v dd3 = v dd4 = 7 v, i dd = 22 00 ma , frequency range = 5.5 gh z to 7.5 ghz . table 1 . parameter symbol min typ max unit test conditions/comments frequency range 5.5 7.5 ghz gain 2 4 2 7 db gain variation over temperature 0.0 1 db/c return loss input 17 db output 1 3 d b output power f or 1 db compression p 1 db 3 5 36 dbm 36 dbm = 4 w saturated p sat 3 6.5 db m at 30% pae output third - order intercept ip3 44 dbm measurement taken at p out / tone = 2 8 dbm supply voltage v dd 5 7.5 v total current i dd 2 2 0 0 ma adjust the gate control voltage ( v gg1 to v gg4 ) between ? 2 v to 0 v to achieve an i dd = 220 0 ma typical t a = 25c, v dd = v dd1 = v dd2 = v dd3 = v dd4 = 7 v, i dd = 2200 ma, frequency range = 7.5 ghz to 8.5 ghz. table 2 . parameter symbol min typ max unit test conditions/comments frequenc y range 7.5 8.5 ghz gain 25 28 db gain variation over temperature 0.009 db/c return loss input 15 db output 13 db output power f or 1 db compression p1db 3 5 36 dbm 36 dbm = 4 w saturated p sat 36.5 dbm at 30% pae o utput third - order intercept ip3 43 dbm measurement taken at p out / tone = 28 dbm supply voltage v dd 5 7.5 v total current i dd 2200 ma adjust the gate control voltage (v gg1 to v gg4 ) between ?2 v to 0 v to achieve an i dd = 2200 ma typical
HMC1121 data sheet rev. a | page 4 of 15 absolute maximum ratings table 3. parameter rating drain voltage bias 8 v rf input power (rfin) 1 24 dbm channel temperature 175c continuous power dissipation, p diss (t a = 85c, derate 227 mw/c above 85c) 20.5 w thermal resistance (r th ) junction to ground paddle 4.4c/w maximum peak reflow temperature (msl3) 2 260c storage temperature range ?65c to +150c operating temperature range ?40c to +85c esd sensitivity (human body model) class 1a, passed 250 v 1 the maximum input power (p in ) is limited to 24 dbm or to the thermal limits constrained by the max imum power dissipation. 2 see the ordering guide section. stresses at or above those listed under absolute maximum ratings may cause permanent damage to the product. this is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. operation beyond the maximum operating conditions for extended periods may affect product reliability. esd caution
data sheet HMC1121 rev. a | page 5 of 15 pin configuration and fu nction descriptions 22 2 1 4 5 3 12 11 nic nic nic nic rfin 6 7 nic nic 8 nic 9 10 nic nic nic nic 21 23 v ref 24 v det 25 nic 26 rfout 27 nic 28 nic 29 nic 30 nic nic nic 15 v dd3 14 v gg3 13 nic 16 nic 17 v gg4 18 nic 19 20 v dd4 nic 32 31 v dd2 nic 33 nic 34 v gg2 35 nic 36 v dd1 37 v gg1 38 nic 39 40 nic nic HMC1121 top view (not to scale) notes 1. nic = no internal connection. 2. exposed pad. exposed pad must be connected to the rf/dc ground. 13529-002 figure 2. pin configuration table 4. pin function descriptions pin no. mnemonic description 1 to 4, 6 to 13, 16, 18, 20 to 22, 25, 27 to 31, 33, 35, 38 to 40 nc no internal connection. these pins and exposed ground pad must be connected to rf/dc ground. 5 rfin rf input. this pin is ac-coupled and matched to 50 . see figure 3 for the rfin interface schematic. 14, 17, 34, 37 v gg3 , v gg4 , v gg2 , v gg1 gate controls for the amplifier. adjust v gg1 through v gg4 to achieve the recommended bias current. external bypass capacitors of 100 pf, 10 nf, and 4.7 f are required. see figure 5 for the v gg1 to v gg4 interface schematic. 15, 19, 32, 36 v dd3 , v dd4 , v dd2 , v dd1 drain biases for the amplifier. external bypass capacitors of 100 pf, 10 nf, and 4.7 f are required. see figure 8 for the v dd1 to v dd4 interface schematic. 23 v ref voltage reference. this pin is the dc bias of the diode biased through the external resistor and is used for the temperature compensation of v det . see figure 7 for the v ref interface schematic. 24 v det voltage detection. this pin is the dc voltage re presenting the rf output power rectified by the diode that is biased through an external resistor. see figure 4 for the v det interface schematic. 26 rfout rf output. this pin is ac-coupled and matched to 50 . see figure 6 for the rfout interface schematic. epad exposed pad. the exposed pad must be connected to rf/dc ground.
HMC1121 data sheet rev. a | page 6 of 15 interface schematics rfin 13529-003 figure 3. rfin interface schematic v det 13529-004 figure 4. v det interface schematic v gg1 , v gg2 , v gg3 , v gg4 13529-005 figure 5. v gg1 to v gg4 interface schematic rfout 13529-006 figure 6. rfout in terface schematic v ref 13529-007 figure 7. v ref interface schematic v dd1 , v dd2 , v dd3 , v dd4 13529-008 figure 8. v dd1 to v dd4 interface schematic
data sheet HMC1121 rev. a | page 7 of 15 typical performance characteristics 40 30 20 10 0 ?10 ?20 ?30 4 6 5 7 8 9 10 response (db) frequency (ghz) s11 s21 s22 13529-009 figure 9. response ( broadband gain and return loss ) vs. frequency for s 2 1, s 11 , and s22 0 ?25 ?20 ?15 ?10 ?5 5 6 7 8 9 return loss (db) frequency (ghz) +85c +25c ?40c 13529-010 figure 10 . input return loss vs. frequency at various temperature s 40 30 32 34 36 38 5 6 7 8 9 p1db (dbm) frequency (ghz) +85c +25c ?40c 13529-0 1 1 figure 11 . p1db vs. frequency at various temperature s 30 20 22 24 26 28 5 6 7 8 9 gain (db) frequency (ghz) +85c +25c ?40c 13529-012 figure 12 . gain vs. frequen cy at various temperature s 0 ?25 ?20 ?15 ?10 ?5 5 6 7 8 9 return loss (db) frequency (ghz) +85c +25c ?40c 13529-013 figure 13 . output return loss vs. frequency at various temperature s 40 30 32 34 36 38 5 6 7 8 9 p1db (dbm) frequency (ghz) 6v 7v 13529-014 figure 14 . p1db vs. frequency at various supply voltage s
HMC1121 data sheet rev. a | page 8 of 15 40 30 32 34 36 38 5 6 7 8 9 p sat (dbm) frequency (ghz) +85c +25c ?40c 13529-015 figure 15 . p sa t vs. frequency at various temperature s 40 30 32 34 36 38 5 6 7 8 9 p1db (dbm) frequency (ghz) 1800ma 2000ma 2200ma 2400ma 13529-016 figure 16 . p1db vs. frequency at various supply current s (i dd ) 48 36 38 42 46 40 44 5 6 7 8 9 ip3 (dbm) frequency (ghz) +85c +25c ?40c 13529-017 figure 17 . output ip3 vs. frequency at various temperature s, p out /tone = 2 8 dbm 40 30 32 34 36 38 5 6 7 8 9 p sat (dbm) frequency (ghz) 6v 7v 13529-018 figure 18 . p sat vs. frequency at various supply voltage s 40 30 32 34 36 38 5 6 7 8 9 p sat (dbm) frequency (ghz) 1800ma 2000ma 2200ma 2400ma 13529-019 figure 19 . p sat vs. frequency at various supply current s (i dd ) 48 36 38 42 46 40 44 5 6 7 8 9 ip3 (dbm) frequency (ghz) 1800ma 2000ma 2200ma 2400ma 13529-020 figure 20 . output ip3 vs. frequency at various supply curre nt s, p out /tone = 2 8 dbm
data sheet HMC1121 rev. a | page 9 of 15 48 36 38 42 46 40 44 5 6 7 8 9 ip3 (dbm) frequency (ghz) 6v 7v 13529-021 figure 21 . output ip3 vs. frequency at various supply voltage s, p out /tone = 28 dbm 60 50 40 30 20 10 0 16 18 20 22 24 26 28 30 32 34 im3 (dbc) p out /tone (dbm) 5.5ghz 6.5ghz 7.5ghz 8.5ghz 13529-022 figure 22 . output third - order intermodula tion ( im3 ) vs. p out /tone at v dd = 7 v 40 0 10 5 15 25 35 20 30 ?14 ?10 ?6 2 ?2 10 6 14 p out (dbm), gain (db), pae (%) input power (dbm) 3000 2900 2800 2700 2600 2500 2400 2300 2200 2100 2000 i dd (ma) p out gain pae i dd 13529-023 figur e 23 . p out , gain, pae, and i dd vs. input power at 7 ghz 60 50 40 30 20 10 0 16 18 20 22 24 26 28 30 32 34 im3 (dbc) p out /tone (dbm) 5.5ghz 6.5ghz 7.5ghz 8.5ghz 13529-024 figure 24 . output im3 vs. p out /tone at v dd = 6 v 60 50 40 30 20 10 0 16 18 20 22 24 26 28 30 32 34 im3 (dbc) p out /tone (dbm) 5.5ghz 6.5ghz 7.5ghz 8.5ghz 13529-025 figure 25 . output im3 vs. p out /tone at v dd = 8 v 40 35 30 25 20 1800 2000 2200 2400 gain (db), p1db (dbm), p sat (dbm) i dd (ma) gain p1db p sat 13529-026 figure 26 . gain , p1db, and p sat vs. supply current (i dd ) at 7 ghz
HMC1121 data sheet rev. a | page 10 of 15 40 35 30 25 20 6.0 6.5 7.0 7.5 8.0 gain (db), p1db (dbm), p sat (dbm) v dd (v) gain p1db p sat 13529-027 figure 27 . gain, p1db, and p sat vs. supply voltage (v dd ) at 7 ghz 20 18 16 14 12 10 ?14 ?10 ?8 ?6 ?4 0 4 6 8 2 ?12 ?2 10 12 power dissipation (w) input power (dbm) 5.5ghz 6.5ghz 7.5ghz 8.5ghz 13529-028 figure 28 . power dissipation vs. input pow er at t a = 85c 0 ?90 ?70 ?50 ?30 ?10 ?80 ?60 ?40 ?20 reverse isolation (db) 5 6 7 8 9 frequency (ghz) +85c +25c ?40c 13529-029 figure 29 . reverse isolation vs. frequency at various temperature s 10 1 0.1 0.01 0.001 ?10 0 10 20 30 40 v ref ? v det (v) output power (dbm) 5.5ghz 7.0ghz 8.5ghz 13529-030 figure 30 . detector voltage (v ref v det ) vs. output power at various frequencies 10 1 0.1 0.01 0.001 ?10 0 10 20 30 40 v ref ? v det (v) output power (dbm) +85c +25c ?40c 13529-031 figure 31 . detector voltage (v ref v det ) vs. output power at various temperatures, at 7 ghz
data sheet HMC1121 rev. a | page 11 of 15 t heory of o peration the HMC1121 is a three - stage, gaas, phemt, mmic, 4 w power amplifier consisting of three gain stages in series. a simplified block diagram is shown in figure 32. the input signal is divided evenly into two ; eac h of these two paths are amplified through three independent gain stages. the amplified signals are then combined at the output. 13529-032 v gg2 v gg1 rfin v dd2 v dd1 rfout v gg4 v gg3 v dd4 v dd3 figure 32 . simplified block diagram the HMC1121 has single - ended input and output ports whose impedances are nominally matched to 50 ? internally over the 5.5 ghz to 8.5 ghz frequency range. consequently, it can directly insert into a 50 ? system with out the need for impedance matching circ uitry . in addition, m ultiple HMC1121 amplifiers can be cascaded back to back without the need of external matching circuitry. similarly, multiple HMC1121 amplifiers can be used with power dividers at the input and power combiners at the output to obtain higher output power levels. the input and output impedances are sufficiently stable vs. variations in temperature and supply voltage that no impedance matching compensation is required. it is critical to supply very low inductance ground connections to the ground pins as well as to the backside exposed pad to ensure stable operation. to ensure the best performance out of the HMC1121 , d o not exceed the absolute maximum ratings.
HMC1121 data sheet rev. a | page 12 of 15 applications informa tion figure 33 shows t he basic connections for operating the HMC1121 and also see the theory of operation section for additional information . the rf input and rf output are ac - coupled by the internal dc block capacitors. recommended bias seq uence follow the reco mmended bias sequencing to avoid damaging the amplifier. d uring power - up the recommended bias sequence during power - up is the following: 1. connect to ground. 2. set v ggx to ? 2 v . 3. set v dd x to 7 v . 4. increase v ggx to achieve a typical i dd = 2200 ma . 5. apply the rf signal . d uring power - down the recommended bias sequence during power - down is the following: 1. turn the rf signal off. 2. decrease v ggx to ? 2 v to achieve a typical i dd = 0 ma . 3. decrease v dd x to 0 v . 4. increase v ggx to 0 v . the bias conditions previously listed (v ddx = 7 v, i dd = 2200 ma), are the recommended operating point to acheive optimum performance. the data used in this datasheet is taken with the recommended bias conditio n s. when u sing the HMC1121 with different bias condition s, different performance may result than what is shown in the typical performance characteristics section. the v det and v ref pins are the output pins for the internal power detector. the v det pin is the dc voltage output pin that represents the rf output power rectified by the internal diode, which is biased through an external resistor. the v ref pin is the dc vol tage output pin that represents the reference diode voltage, which is biased through an external resistor. this voltage is then used to compensate for the temperature variation effects on both diodes. a typical circuit is shown in the typical application circuit section that reads out the output voltage and represents the rf output power is shown in figure 33. typical application circuit j1 rfin j2 rfout v gg3 v dd3 + c13 10nf c6 100pf r3 20 r4 20 c15 10nf c7 100pf c16 10nf c22 4.7f + c23 4.7f v gg4 c8 100pf c21 4.7f + c22 4.7f + c13 10nf c5 100pf 100k 100k 10k 10k 10k 10k +5v +5v ?5v v out = v ref ? v det suggested circuit r1 20 c1 100pf c9 10nf c17 4.7f + v gg1 c3 100pf c11 10nf c18 4.7f + v dd1 r2 20 c2 100pf c4 100pf c10 10nf c12 10nf + c19 4.7f v gg2 v dd4 + c20 4.7f v dd2 22 2 1 4 5 3 12 11 nic nic nic nic 6 7 nic nic 8 nic 9 10 nic nic nic nic 21 23 v ref 24 v det 25 nic 26 27 nic 28 nic 29 nic 30 nic nic nic 15 v dd3 14 v gg3 13 nic 16 nic 17 v gg4 18 nic 19 20 v dd4 nic 32 31 v dd2 nic 33 nic 34 v gg2 35 nic 36 v dd1 37 v gg1 38 nic 39 40 nic nic HMC1121 13529-033 figure 33 . typical application circuit
data sheet HMC1121 rev. a | page 13 of 15 evaluation board the HMC1121 evaluation printed circuit board (pcb) is a 2-layer board that was fabricated using a rogers 4350 and best practices for high frequency rf design. the rf input and rf output traces have a 50 characteristic impedance. the pcb is attached to a heat sink by a sn96 solder, which provides a low thermal resistance path. components are mounted using sn63 solder, allowing rework of the surface-mount components without compromising the circuit board to heat sink attachment. the evaluation pcb and populated components operate over the ?40c to +85c ambient temperature range. during operation, attach the evaluation pcb to a temperature controlled plate to control the temperature. for proper bias sequence, see the applications information section. see figure 35 for the HMC1121 evaluation board schematic. a fully populated and tested evaluation board, which is shown in figure 34, is available from analog devices, inc., upon request. 13529-034 figure 34. HMC1121 evaluation board bill of materials table 5. item description j1, j2 pcb mount sma rf connector, johnson pn 142-07010851 j3, j4 dc pins j5, j6 rf connectors for thru line; not populated c1 to c8 100 pf capacitors, 0402 package c9 to c16 10 nf capacitors, 0402 package c17 to c24 4.7 f capacitor, case a r1 to r4 20 resistors, 0402 package r5, r6 100 k resistors, 0402 package u1 HMC1121lp6ge heat sink used for thermal transfer from the HMC1121lp6ge amplifier pcb 600-01061-00 evaluation board; circuit board material: rogers 4350
HMC1121 data sheet rev. a | page 14 of 15 e valuation b oard s chematic 13529-035 j1 j2 vg3 vd3 + c14 10nf c6 100pf r3 20 r4 20 c15 10nf c7 100pf c16 10nf c24 4.7f + c23 4.7f vg4 c8 100pf c21 4.7f + c22 4.7f + c13 10nf c5 100pf r1 20 c1 100pf c9 10nf c17 4.7f + vg1 c3 100pf c11 10nf c18 4.7f + vd1 r2 20 c2 100pf c4 100pf c10 10nf c12 10nf + c19 4.7f vg2 vd4 + c20 4.7f vd2 2 1 4 5 3 12 11 nc nc nc nc rfin u1 6 7 nc nc 8 nc 9 10 nc nc nc nc vref vdet 25 24 23 22 21 rfout nc nc nc nc 30 12 j4 j3 87759-1250 10 8 6 4 2 vd4 vd5 vd6 vg4 vd3 vg3 11 9 7 5 3 1 29 28 27 26 nc nc nc 15 vd3 14 vg3 13 nc 16 nc 17 vg4 18 nc 19 20 vd4 nc 32 31 33 34 35 36 37 38 39 40 vd2 nc nc vg2 nc vd1 vg1 nc nc nc rfin rfout j6 depop j5 depop thrucal r5 100k vdet vref r6 100k 87759-0850 8 6 4 2 vg1 vd1 vg2 vd2 7 5 3 1 figure 35 . hm c1121 evaluation b oard schematic
data sheet HMC1121 rev. a | page 15 of 15 outline dimensions 10-19-2017-a 0.50 bsc bottom view top view side view pin 1 indic a t or exposed pad 0.05 max 0.02 nom 0.20 ref 4.50 ref coplanarity 0.08 0.30 0.25 0.20 6.10 6.00 sq 5.90 0.90 0.85 0.80 0.35 0.30 0.25 0.20 min 4.75 4.70 sq 4.65 compliant to jedec standards mo-220-vjjd-5 4 0 1 1 1 1 0 2 0 2 1 3 0 3 1 pkg-004893 for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. sea ting plane pin 1 indic a t or area options (see detail a) detail a (jedec 95) figure 36 . 40 - lead lead frame chip scale package [lfcsp] 6 mm 6 mm body and 0.85 mm package height (hcp - 40 - 1) dimensions shown in millimeters ordering guide model 1 temperat ure msl rating 2 package description 3 package option HMC1121lp6ge ?40c to +85c msl3 40 - lead lead frame chip scale package [lfcsp] hcp -40-1 HMC1121lp6getr ?40c to +85c msl3 40 - lead lead frame chip scale package [lfcsp] hcp -40-1 ev1HMC1121lp6g evalu ation board 1 the HMC1121lp6ge and the HMC1121lp6getr are rohs - co mpliant parts. 2 see the absolute maximum ratings section for additional details. 3 the HMC1121lp6ge and the HMC1121lp6getr are low stress injection molded plastic and their lead finish is 100% matte sn. ? 2016 C 2017 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d13529 - 0 - 10/17(a)

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